The DLX is a reduced instruction set computer (RISC) processor architecture. It is mainly a cleaner, simpler MIPS architecture, with a simple 32-bit load-store design, and intended mainly for education, as are Donald Knuth's MIX and MMIX architectures. All three are widely used in college-level computer architecture courses. DLX was introduced in the textbook "Computer Architecture: A Quantitative Approach", by John L. Hennessy and David A. Patterson, the main designers of the MIPS and Berkeley RISC designs, respectively, which are the two benchmark RISC designs. DLX Processors Components Hardware Computers.
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. (wikipedia)
- DLX A RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal...
- Dancing Links The technique suggested by Donald Knuth to efficiently implement his Algorithm X. Algorithm X is...
- Dlx (gene) A family of homeodomain transcription factors which are related to the Drosophila distal-less gene.
- 560 A leap year starting on Thursday of the Julian calendar.
- MMIX 2009: A RISC Computer for the Third Millennium www
Donald E. 2009: A RISC Computer for the Third Millennium. Knuth's new 64-bit processor for the new volumes of his landmark series 'The Art of Computer Programming'. MIX has become more than only a book example, so MMIX should too. Description, news.
- Diagram, Superscalar DLX Processor www
Diagram, DLX Processor, description, download. Superscalar DLX Processor.
- Introductory Implementation of 5-stage DLX Pipeline www
Introductory tutorial with definitions, 5-stage DLX Pipeline, explanations, examples to show basic pipelining ideas; applet simulation lets users choose instructions to run, and see how pipeline works from direct experience. Implementation of 5-stage DLX Pipeline.
- Director David R. Kaeli, Professor www
Director of Northeastern University Computer Architecture Research Laboratory, Kaeli, Professor, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links. David R. Kaeli, Professor.
- By The DLX Instruction Set Architecture Handbook www
By Philip M. DLX Instruction Set Architecture Handbook. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal. The DLX Instruction Set Architecture Handbook.
- DLXOS Introduction to Operating Systems www
DLXOS information needed for programming, Operating Systems, from introductory course on OSs. Introduction to Operating Systems.
- Documents: DLX Information www
Documents: getting started, Information, instruction set summary and description, simulator manual. DLX Information.
- Information Norman Matloff's DLX Tutorial www
Information on DLX processor simulator and compiler, Matloff's DLX Tutorial, DLXsim, interactive program, loads assembly programs and simulates operation of computer on them, single-stepping or continuous execution. Norman Matloff's DLX Tutorial.
- VHDL DLX in VHDL www
VHDL model of processor; most instructions use 5 clock cycles to run, VHDL, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download. DLX in VHDL.
- Program WinDLX www
Program for MS Windows, WinDLX, an assembly interpreter for DLX assembly language; instructions, source code, downloads. By Javier Echaiz, National University of the South. WinDLX.
- Class The DLX Processor www
Class overview with tables (instruction format, DLX Processor, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland. The DLX Processor.
- Master's Out of Order Execution www
Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Order Execution. Uses DLX. HTML, PS, GZ, PDF. Out of Order Execution.
- Photo DLX CPU in SCMOS www
Photo with descriptions. DLX CPU in SCMOS.
- Documents DLX Implementation at MSU www
Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), Implementation at MSU, MSU Engineering Research Center; used as design driver to help validate standard cell libraries. DLX Implementation at MSU.
- Tables DLX Instruction Slides www
Tables of instructions, Instruction Slides, categorized, as PDF slides. By Guy Even, Tel Aviv University. DLX Instruction Slides.
- ASynchronous, ASPIDA Project www
ASynchronous, Project, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware. ASPIDA Project.
- Encyclopedia Wikipedia: DLX www
Encyclopedia article with links to many related topics. Wikipedia: DLX.
- Academic AcadOS www
Academic Operating System, AcadOS, goals: to expose students to more modern ideas than older OSs, to basic OS mechanisms, to OS and language design and prototyping; old version, ideas for new microkernel version. AcadOS.
- Not NACHOS www
Not Another Completely Heuristic Operating System: teaching OS coded in C++ subset, NACHOS, developed at UC Berkeley for OS and Systems Programming classes; now used worldwide. Descriptions, FAQ, port and bug lists, assignments, downloads. [Open Source] NACHOS.
- A JUDO www
A programming environment designed to help teach beginners and children how to program. JUDO.
- Facilitating Technology Without Borders www
Facilitating innovative information technology advancements that support the development of open societies and economics in developing countries. Technology Without Borders.
- Compiler Zngr L www
Compiler of the theoretical language L, L, which is used as a simple language for teaching computation theory Zngr L.
- Makes SGP Systems www
Makes Baltie line of educational, Systems, graphic, object-oriented visual languages, for kids through adults; DOS and Windows versions. Czech Republic. SGP Systems.
- Instruction Sulima www
Instruction set architecture simulator for MIPS64; supports U4600 platform, Sulima, based on an R4700 processor. Sulima.
- Makes MIPS Technologies, Inc. www
Makes popular RISC CPU used in consumer electronics, Technologies, Inc., Sony PlayStations, Cisco routers, some SGI computers. Initiated MIPS instruction set. Now an independent company developing processor cores and intellectual property for license. MIPS Technologies, Inc..
- Uses BeOS MIX www
Uses BFiles for 18 of 20 MIX I/O devices, MIX, each MIX I/O instruction spawns a Be thread to do operation while MIX keeps computing. Has MIX Go button, unlike some MIX emulators, coded in C++. BeOS MIX.
- From John Mashey on RISC/CISC www
John Mashey on RISC/CISC.
- Defines What is RISC? www
Defines term, RISC?, lists other webpages. Webopedia. What is RISC?.
- CPU Powerleap Products www
CPU upgrade expert with product briefs, Products, support, discussion forums and compatibility database. Powerleap Products.
- An MicroDesign Resources www
An information services company focused on enabling technology for personal computers and the high-performance microprocessor industry. Resources. Our work is aimed at engineers and others who need to understand and select new technologies. MicroDesign Resources.
- Alexa: DLX Processors
Alexa Directory Top Sites: DLX Processors
- DMOZ: DLX Processors
dmoz.org Directory: DLX Processors