The DLX is a reduced instruction set computer (RISC) processor architecture. It is mainly a cleaner, simpler MIPS architecture, with a simple 32-bit load-store design, and intended mainly for education, as are Donald Knuth's MIX and MMIX architectures. All three are widely used in college-level computer architecture courses. DLX was introduced in the textbook "Computer Architecture: A Quantitative Approach", by John L. Hennessy and David A. Patterson, the main designers of the MIPS and Berkeley RISC designs, respectively, which are the two benchmark RISC designs. DLX Processors Components Hardware Computers.
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. (wikipedia)
- DLX A RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal...
- Dancing Links The technique suggested by Donald Knuth to efficiently implement his Algorithm X. Algorithm X is...
- Dlx (gene) A family of homeodomain transcription factors which are related to the Drosophila distal-less gene.
- 560 A leap year starting on Thursday of the Julian calendar.
- By The DLX Instruction Set Architecture Handbook www
By Philip M. DLX Instruction Set Architecture Handbook. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal. The DLX Instruction Set Architecture Handbook.
- Director David R. Kaeli, Professor www
Director of Northeastern University Computer Architecture Research Laboratory, Kaeli, Professor, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links. David R. Kaeli, Professor.
- ASynchronous, ASPIDA Project www
ASynchronous, Project, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware. ASPIDA Project.
- Encyclopedia Wikipedia: DLX www
Encyclopedia article with links to many related topics. Wikipedia: DLX.
- Photo DLX CPU in SCMOS www
Photo with descriptions. DLX CPU in SCMOS.
- Information Norman Matloff's DLX Tutorial www
Information on DLX processor simulator and compiler, Matloff's DLX Tutorial, DLXsim, interactive program, loads assembly programs and simulates operation of computer on them, single-stepping or continuous execution. Norman Matloff's DLX Tutorial.
- Tables DLX Instruction Slides www
Tables of instructions, Instruction Slides, categorized, as PDF slides. By Guy Even, Tel Aviv University. DLX Instruction Slides.
- Documents: DLX Information www
Documents: getting started, Information, instruction set summary and description, simulator manual. DLX Information.
- Introductory Implementation of 5-stage DLX Pipeline www
Introductory tutorial with definitions, 5-stage DLX Pipeline, explanations, examples to show basic pipelining ideas; applet simulation lets users choose instructions to run, and see how pipeline works from direct experience. Implementation of 5-stage DLX Pipeline.
- Master's Out of Order Execution www
Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Order Execution. Uses DLX. HTML, PS, GZ, PDF. Out of Order Execution.
- Documents DLX Implementation at MSU www
Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), Implementation at MSU, MSU Engineering Research Center; used as design driver to help validate standard cell libraries. DLX Implementation at MSU.
- VHDL DLX in VHDL www
VHDL model of processor; most instructions use 5 clock cycles to run, VHDL, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download. DLX in VHDL.
- Diagram, Superscalar DLX Processor www
Diagram, DLX Processor, description, download. Superscalar DLX Processor.
- Class The DLX Processor www
Class overview with tables (instruction format, DLX Processor, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland. The DLX Processor.
- DLXOS Introduction to Operating Systems www
DLXOS information needed for programming, Operating Systems, from introductory course on OSs. Introduction to Operating Systems.
- Program WinDLX www
Program for MS Windows, WinDLX, an assembly interpreter for DLX assembly language; instructions, source code, downloads. By Javier Echaiz, National University of the South. WinDLX.
- Teachable Topsy www
Teachable Operating System: tiny multithreaded messaging microkernel, Topsy, in ANSI C; protected threads, memory managed, and thread/process control. From undergraduate course on concurrency, device programming, OS concepts. Descriptions, documents, theses, downloads, contacts, links. [Open Source, GPL] Topsy.
- Port, Nachos/486 www
- A Intertech Inc. www
A company dedicated to Java and Microsoft hands-on developer training. Inc.. It informs about training programs, consulting services and job offers. Intertech Inc..
- Text Deitel & Associates, Inc. www
Text books and training courses in Java, & Associates, Inc., C, C++, Internet and other programming technologies. Deitel & Associates, Inc..
- Makes SGP Systems www
Makes Baltie line of educational, Systems, graphic, object-oriented visual languages, for kids through adults; DOS and Windows versions. Czech Republic. SGP Systems.
- Compiler Zngr L www
Compiler of the theoretical language L, L, which is used as a simple language for teaching computation theory Zngr L.
- Makes MIPS Technologies, Inc. www
Makes popular RISC CPU used in consumer electronics, Technologies, Inc., Sony PlayStations, Cisco routers, some SGI computers. Initiated MIPS instruction set. Now an independent company developing processor cores and intellectual property for license. MIPS Technologies, Inc..
- Instruction Sulima www
Instruction set architecture simulator for MIPS64; supports U4600 platform, Sulima, based on an R4700 processor. Sulima.
- MIX GNU MDK www
MIX Development Kit, MDK, emulates MIX, MIXAL; with compiler, virtual machine, GUI, Guile interpreter, Emacs mode, Elisp program to run programs in Emacs window. GNU MDK.
- MIXAL MixNet www
MIXAL compiler for Microsoft . MixNet.NET framework. Emits .NET executable files. Source code is C#. Public Domain. MixNet.
- From John Mashey on RISC/CISC www
John Mashey on RISC/CISC.
- Today's Beyond RISC: The Post-RISC Architecture www
Today's RISC processors are so far from RISC roots that they are no longer truly RISC. RISC: The Post-RISC Architecture. Michigan State University, Department of Computer Science. Beyond RISC: The Post-RISC Architecture.
- Floating ClearSpeed www
Floating point accelerator, ClearSpeed, coprocessor and data parallel processing for HPC, scientific and embedded computer chips. Programmed easily in C language. ClearSpeed.
- Growing Central Processing Unit www
Growing article, Processing Unit, with links to many related topics. [Wikipedia] Central Processing Unit.
- Alexa: DLX Processors
Alexa Directory Top Sites: DLX Processors
- DMOZ: DLX Processors
dmoz.org Directory: DLX Processors